In conventional integrated circuit manufacturing processes, wafers comprising a semiconductor substrate (typically silicon) having a metal pattern deposited thereon are first coated with an oxide layer. A layer known as a "resist" is then coated on the oxide layer. In order to deposit conductive material directly onto a region of the substrate, or onto a region of the metal pattern deposited on the substrate, the oxide and resist layers above such region must be removed. The channel through the oxide and resist layers formed by such removal is known as a "via." Various conventional etching processes have been employed to produce vias.
For example, a conventional anisotropic plasma etch process produces vias having sidewalls substantially perpendicular to the plane of the resist and oxide layers ("non-tapered" vias). Such non-tapered vias are produced in this process by exposing a coated wafer to an oxide etch plasma, typically consisting of CHF.sub.3, C.sub.2 F.sub.6, or a CHF.sub.3 /C.sub.2 F.sub.6 mixture. Such fluorocarbons are often used as the oxide etch substance since they are "selective" to silicon in the sense that they will not erode silicon over a characteristic time period in which they will erode the resist and oxide layers coated on a silicon substrate.
However, poor metal coverage typically results when metal is deposited in the non-tapered vias produced by such conventional processes. This phenomenon can be explained by recognizing that in a typical metal deposition process, the metal coverage is limited by the amount of metal arriving to the inside of the via through the via opening and by the ability of the metal to distribute evenly on the vertical (non-tapered) via sidewalls. We have found that when a metal film consisting of a TiW/Al/TiW sandwich is sputtered in a conventional manner inside a conventional cylindrical via having 1.0 micron depth and 1.5 micron diameter, the resulting metal coverage on the via sidewalls is often less than twenty percent.
One technique that has been tried for improving metal coverage on the sidewalls is to produce a via whose sidewalls have a tapered profile. Such a tapered profile via can be produced by employing a conventional resist erosion plasma etch process. In such a resist etch process, the resist and the oxide layer are simultaneously eroded (with a fixed ratio of vertical etching rate to lateral etching rate) by exposure to a plasma consisting of a mixture of oxygen and an oxide etch substance such as CHF.sub.3, C.sub.2 F.sub.6, or a CHF.sub.3 /C.sub.2 F.sub.6 mixture. Given a selected mixture of oxide etch substance and oxygen, the slope of the via sidewalls produced in such process is fixed. Thus, variations in the resist or oxide layer thickness (or in the thickness of metal deposits or other topographic features on the semiconductor substrate) will vary the bottom diameter (also referred to as the critical dimension or "CD") of the vias produced by such process, in a manner that will be readily appreciated with reference to FIG. 1.
Three vias (identified by numerals 41, 42, and 43) of the type produced by a conventional resist erosion plasma etch process are shown in FIG. 1. FIG. 1 is a cross-sectional view of semiconductor substrate 10, which is coated by oxide layer 20 and resist 30. Metal portion 14 is deposited on substrate 10, and metal portion 15 is deposited on topographic feature 16 on substrate 10. Since the plane of FIG. 1 is perpendicular to the planar interface between substrate 10 and oxide layer 20, the cross-section of each of vias 41, 42, and 43 is shown in FIG. 1. Vias 41, 42, and 43 may be frusto-conical or conical, or may be laterally elongated with a longitudinal axis perpendicular to the plane of FIG. 1. Vias 41, 42, and 43 have been produced by exposing layers 20 and 30 above metal portion 15, metal portion 16, and region 17 on the surface of substrate 10, respectively, to the resist etching plasma for the same time period. The critical dimension (or "CD") of via 41 extending to metal portion 14 has magnitude A, which is less than the CD (having magnitude B) of via 42 extending to metal portion 15. Due to an increased thickness of oxide 20 above region 17, via 43 above region 17 does not extend all the way to region 17, so that via 43 would need to be etched for an additional time period (i.e. would need to be "overetched") in order to reach substrate 10. However, if via 43 were overetched for a sufficient time duration so that it reached region 17, the diameter of the portion of such overetched version of via 43 farthest from substrate 10 (the diameter of the "opening" of overetched via 43) would undesirably be far greater than the opening diameter (length C) of via 41 or 42.
Improved metal coverage can alternatively be achieved by using conventional wet etch processes or sequential dry and wet etch processes. Two vias of the type produced by this class of process are shown in FIG. 2. The liquid chemicals (typically acids) employed in wet etching will erode unimaged portions of the resist (indicated by dashed resist portions 34 and 35) but will not react with imaged portions of the resist such as resist portions 31, 32, and 33. The wet etching process will accordingly undercut an imaged resist portion such as portion 31 if allowed to proceed for a sufficiently long time. More generally, because wet etching is an isotropic etching process (i.e., the vertical and lateral etching rates are substantially the same), wet etching is unsuitable for etching vias having high aspect ratio, where the phrase "aspect ratio" denotes the ratio of via depth (i.e., "vertical" extent in the direction perpendicular to the plane of the semiconductor substrate) to via lateral dimension.
It has not been known until the present invention how to produce vias by a plasma etching process in a manner eliminating both the above-described problems of poor metal coverage and CD variation. Nor has it been known until the present invention how to eliminate both the problem of poor metal coverage and the problem of CD variation in a process for etching high aspect ratio vias.